MPC8280 datasheet(528/1386 Pages) FREESCALE

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Secondary (L2) Cache Support

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

12-2

Freescale Semiconductor

Figure 12-1 shows a MPC8280 connected to a MPC2605 integrated L2 cache in copy-back mode.

Figure 12-1. L2 Cache in Copy-Back Mode

12.1.2

Write-Through Mode

In write-through mode, cacheable write operations are performed to both the L2 cache and to main

memory. Since every cacheable write operation goes to the L2 cache and to main memory, write operation

latency is the same as an ordinary memory write transaction. In write-through mode, cacheable read

operations that hit in the L2 cache are serviced from the L2 cache without requiring a memory transaction

DBG

TS, TT[0–4], TBST, TSIZ[1–3]

A[0–31]

CI, WT, GBL, TA, DBB, TEA

CPU_BR, CPU_BG, CPU_DBG

D[0–63]

MPC8280

L2BR

L2DBG

TS, TT[0–4], TBST, TSIZ[0–2]]

CI, WT, GBL, TA, DBB, TEA

AACK, ARTRY

CPU_BR,CPU_BG,CPU_DBG

L2_CLAIM

L2_HIT

A[0–31]

D[0–63]

Memory Controller

SDRAM Main Memory

Latch

MUX

I/O Devices

MPC2605

L2BG

TSIZ[0]

(pull down)

(pull up)

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