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MPC8280 bảng dữ liệu(PDF) 523 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8280
Giải thích chi tiết về linh kiện  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MPC8280 bảng dữ liệu(HTML) 523 Page - Freescale Semiconductor, Inc

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Memory Controller
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
11-103
is sampled in the GPCM or after each READ/WRITE command in the SDRAM machine (the SDRAM
machine uses BADDR only for port sizes of 16 or 8 bits).
11.9.5
External Masters Timing
External and internal masters have similar memory access timings. However, because it takes more time
to decode the addresses of external masters, memory accesses by external masters start one cycle later than
those of internal masters.
As soon as the external master asserts TS, the memory controller compares the address with each of its
defined valid banks. If a match is found, the memory controller asserts the address latch enable (ALE) and
control signals to the memory devices. The memory controller asserts PSDVAL for each data beat to
indicate data beat termination on write transactions and data valid on read transactions.
The 60x bus is pipelined. The ALE pins control the external latch that latches the address from the 60x bus
and keeps the address stable for the memory access. The memory controller asserts ALE only on the start
of new memory controller access.
Figure 11-84 shows the pipelined bus operation in 60x-compatible mode.



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