MPC8280 datasheet(496/1386 Pages) FREESCALE

496 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-76

Freescale Semiconductor

Figure 11-63 and the timing diagrams in Figure 11-60 show how UPMs control CS signals.

Figure 11-63. CS Signal Selection

11.6.4.1.2

Byte-Select Signals (B

xTx)

BRx[MS] of the accessed memory bank selects a UPM on the currently requested cycle. The selected UPM

affects only the assertion and negation of the appropriate BS signal; its timing as specified in the RAM

word. The BS signals are controlled by the port size of the accessed bank, the transfer size of the

transaction, and the address accessed. Figure 11-64 shows how UPMs control BS signals.

Figure 11-64. BS Signal Selection

The uppermost byte select (BS0) indicates that D[0–7] contains valid data during a cycle. Likewise, BS1

indicates that D[8–15] contains valid data, BS2 indicates that D[16–23] contains valid data, and BS3

indicates that D[24–31] contains valid data during a cycle, and so forth. Note that for a refresh timer

request, all the BS signals are asserted/negated by the UPM.

UPMA/B/C

SDRAM

GPCM

MUX

BRx[MS]

CS3

CS4

CS5

CS6

CS7

CS8

Switch

Bank Selected

CS9

CS10

CS11

CS0

CS1

CS2

UPMA

MUX

MS/BS

BS0

BS1

BS2

BS3

Bank Selected

BRx[PS]

A[29–31]

TSIZ

Byte-Select

Logic

UPMB

UPMC

BS4

BS5

BS6

BS7

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