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MPC8280 bảng dữ liệu(PDF) 489 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8280
Giải thích chi tiết về linh kiện  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 bảng dữ liệu(HTML) 489 Page - Freescale Semiconductor, Inc

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Memory Controller
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
11-69
Figure 11-59. Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1)
Clock Ratios
The state of the external signals may change (if specified in the RAM array) at any positive edge of T1,
T2, T3, or T4 (there is a propagation delay specified in the Hardware Specifications). Note however that
only the CS signal corresponding to the currently accessed bank is manipulated by the UPM pattern when
it runs. The BS signal assertion and negation timing is also specified for each cycle in the RAM word;
which of the four BS signals are manipulated depends on the port size of the specified bank, the external
address accessed, and the value of TSIZn. The GPL lines toggle as programmed for any access that
initiates a particular pattern, but resolution of control is limited to T1 and T3.
Figure 11-60 shows how CSx, GPL1, and GPL2 can be controlled. A word is read from the RAM that
specifies on every clock cycle the logical bits CST1, CST2, CST3, CST4, G1T1, G1T3, G2T1, and G2T3.
These bits indicate the electrical value for the corresponding output pins at the appropriate timing.
CLKIN
T1
T2
T3
T4



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