MPC8280 datasheet(482/1386 Pages) FREESCALE

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Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-62

Freescale Semiconductor

Figure 11-54. External Termination of GPCM Access

11.5.3

Boot Chip-Select Operation

Boot chip-select operation allows address decoding for a boot ROM before system initialization. The CS0

signal is the boot chip-select output; its operation differs from the other external chip-select outputs on

system reset. When the MPC8280 internal core begins accessing memory at system reset, CS0 is asserted

for every address in the boot address range, unless an internal register is accessed. The address range is

configured during reset.

The boot chip-select also provides a programmable port size during system reset by using the

configuration mechanism described in Section 5.4, “Reset Configuration.” The boot chip-select does not

provide write protection. CS0 operates this way until the first write to OR0 and it can be used as any other

chip-select register once the preferred address range is loaded into BR0. After the first write to OR0, the

boot chip-select can be restarted only on hardware reset. Table 11-33 describes the initial values of the boot

bank in the memory controller.

Table 11-33. Boot Bank Field Values after Reset

Setting

BR0

From hard reset configuration word. See Section 5.4.1, “Hard Reset Configuration Word.”

DECC

000

EMEMC From hard reset configuration word. See Section 5.4.1, “Hard Reset Configuration Word.”

Clock

Address

BCTL

GTA

PSDVAL

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