MPC8280 datasheet(475/1386 Pages) FREESCALE

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Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-55

Figure 11-42. GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0)

11.5.1.2

Chip-Select and Write Enable Deassertion Timing

Figure 11-43 shows a basic connection between the MPC8280 and a static memory device. Here, CS is

connected directly to CE of the memory device. The WE signals are connected to the respective W signal

in the memory device where each WE corresponds to a different data byte.

Figure 11-43. GPCM Memory Device Interface

As Figure 11-45 shows, the timing for CS is the same as for the address lines. The strobes for the

transaction are supplied by OE or WE, depending on the transaction direction (read or write). ORx[CSNT]

controls the timing for the appropriate strobe negation in write cycles. When this attribute is asserted, the

strobe is negated one quarter of a clock before the normal case. For example, when ACS = 00 and

CSNT = 1, WE is negated one quarter of a clock earlier, as shown in Figure 11-44.

Clock

Address

PSDVAL

R/W(BCTL0)

Data

ACS = 11

ACS = 10

Address

Data

MEMORY

Data

Address

MPC8280

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