MPC8280 datasheet(360/1386 Pages) FREESCALE

360 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-52

Freescale Semiconductor

9.11.2.9

PCI Bus Cache Line Size Register

Figure 9-41 and Table 9-28 describe the PCI bus cache line size register.

Figure 9-41. PCI Bus Cache Line Size Register

9.11.2.10 PCI Bus Latency Timer Register

Figure 9-42 and Table 9-29 describe the PCI bus latency timer register.

Figure 9-42. PCI Bus Latency Timer Register

Field

CLS

Reset

0000_0000

R/W

Addr

0x0C

Table 9-28. PCI Bus Cache Line Size Register Description

Bits

Name

Description

7–0

Cache line size

Represents the cache line size of the system in terms of 32-bit words (eight 32-bit

words = 32 bytes). This register is read-write; however, an attempt to program this

Field

Reset

0000_0000

R/W

Addr

0x0D

Table 9-29. PCI Bus Latency Timer Register Description

Bits

Name

Description

7–3

Latency timer

Represents the maximum number of PCI clocks that the device, when mastering

a transaction, holds the bus after PCI bus grant has been negated. The value is

in PCI clocks. Refer to the PCI 2.2 specification for the rules by which the PCI bus

interface unit completes transactions when the timer has expired.

2–0

Read-only least-significant bits of the latency timer. (The latency timer value is

programmed in multiples of eight.)

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