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MPC8280 bảng dữ liệu(PDF) 353 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8280
Giải thích chi tiết về linh kiện  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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MPC8280 bảng dữ liệu(HTML) 353 Page - Freescale Semiconductor, Inc

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PCI Bridge
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
9-45
9.11.2
PCI Bridge Configuration Registers
The PCI Local Bus Specification defines the configuration registers from 0x00 through 0x3F. Additionally,
the PCI bridge specifies these additional registers: the PCI function register (at offset 0x44), the PCI arbiter
control register (at offset 0x46), and the PCI Hot Swap register block (at offset 0x48). Table 9-19 and
Figure 9-32 shows the PCI configuration registers provided by the PCI bridge for the PCI bus.
Note the following sections that apply to all PCI configuration registers (they appear immediately after the
descriptions of individual registers):
•
Section 9.11.2.26, “PCI Configuration Register Access from the Core,” on page 9-62
•
Section 9.11.2.27, “PCI Configuration Register Access in Big-Endian Mode,” on page 9-62
•
Section 9.11.2.28, “Initializing the PCI Configuration Registers,” on page 9-64
Table 9-19. PCI Bridge PCI Configuration Registers
Address
(offset)
Register
Access
Reset
Section/Page
00
Vendor ID
R
0x1057
9.11.2.1/9-47
02
Device ID
R
0x18C0
9.11.2.2/9-47
04
PCI command
R/W
Mode-dependent
9.11.2.3/9-47
06
PCI status
Read/bit-reset
0x00B0
9.11.2.4/9-48
08
Revision ID
R
Rev-dependent
9.11.2.5/9-50
09
Standard programming interface
R
Mode-dependent
9.11.2.6/9-50
0A
Subclass code
R
0x00
9.11.2.7/9-51
0B
Class code
R
Mode-dependent
9.11.2.8/9-51
0C
Cache line size
R/W
0x00
9.11.2.9/9-52
0D
Latency timer
R/W
0x00
9.11.2.10/9-52
0E
Header type
R
0x00
9.11.2.11/9-53
0F
BIST control
R
0x00
9.11.2.12/9-53
10
PIMMR base address register
R/W
0x
nnnn_0000
9.11.2.13/9-53
14
GPL base address register 0
R/W
0x0000_0000
9.11.2.14/9-54
18
GPL base address register 1
R/W
0x0000_0000
9.11.2.14/9-54
1C
Reserved
—
—
—
2C
Sub system vendor ID
R/W
0x0000
9.11.2.15/9-55
2E
Sub system device ID
R/W
0x0000
9.11.2.16/9-56
30
Reserved
—
—
—
34
Capabilities pointer
R
0x48
9.11.2.17/9-56
35
Reserved
—
—
—
3C
Interrupt line
R/W
0x00
9.11.2.18/9-57
3D
Interrupt pin
R
0x01
9.11.2.19/9-57



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