MPC8280 datasheet(338/1386 Pages) FREESCALE

338 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-30

Freescale Semiconductor

9.11.1.1

Message Unit (I2O) Registers

Message unit registers are described in Section 9.12, “Message Unit (I2O),” on page 9-66.

9.11.1.2

DMA Controller Registers

DMA registers are described in Section 9.13, “DMA Controller,” on page 9-86.

9.11.1.3

PCI Outbound Translation Address Registers (POTAR

The PCI outbound translation address registers (POTARx), shown in Figure 9-17, select the starting

addresses in PCI address space for locally generated transactions that hit within the outbound translation

windows. The new translated address is created by concatenating the transaction offset to this translation

address. Refer to Section 9.10.2.2, “PCI Outbound Translation.”

Figure 9-17. PCI Outbound Translation Address Registers (POTAR

0x108E0

PCI inbound comparison mask register 1 (PICMR1)

R/W

0x0000_0000

9.11.1.17/9-43

0x108E8

PCI inbound translation address register 0 (PITAR0)

R/W

0x0000_0000

9.11.1.15/9-42

0x108F0

PCI inbound base address register 0 (PIBAR0)

R/W

0x0000_0000

9.11.1.16/9-42

0x108F8

PCI inbound comparison mask register 0 (PICMR0)

R/W

0x0000_0000

9.11.1.17/9-43

0x10900

PCI CFG_ADDR

R/W

undefined

9.9.1.4.4/9-15

0x10904

PCI CFG_DATA

R/W

0x0000_0000

9.9.1.4.4/9-15

0x10908

PCI INT_ACK

R/W

undefined

9.9.1.4.7/9-17

Field

—

Reset

0000_0000_0000_0000

R/W

Addr

0x10802 (POTAR0); 0x1081A (POTAR1); 0x10832 (POTAR2)

Field

Reset

0000_0000_0000_0000

R/W

Addr

0x10800 (POTAR0); 0x10818 (POTAR1); 0x10830 (POTAR2)

Table 9-3. Internal Memory Map (continued)

Address

(offset)

Access

Reset

Section/Page

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