MPC8280 datasheet(330/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-22

Freescale Semiconductor

•

If the transaction address is within one of the two inbound PCI translation windows, the transaction

is sent to the core side of the PCI bridge with address translation.

This window is provided for the PCI master to access the MPC8280's

internal (dual port) registers/area. Its size is assumed to be fixed at 128K

bytes. It translates to the MPC8280's IMMR value for the upper bits of the

address. This way, the PCI master can access any of the PCI bridge registers

(DMA/MU, etc.) without wasting an inbound translation window. In effect,

it suggests that we have a total of three inbound windows, 2 with ATUs and

one with PIMMR.

An address decode flow chart for transactions from a PCI bus master to the PCI bridge is shown in

Figure 9-12.

Figure 9-12. Address Decode Flow Chart for PCI Mastered Transactions

Yes

PCI mastered

transaction

Hit

PIMMR

Yes

(1): IMMR+0x10400

≤ addr ≤ IMMR+0x10bff

Hit

Inbound ATU

No DEVSEL

Translate the

address

Hit PCI

internal registers

Yes

Hit

IMMR

Yes

Execute register

access to

PCI interface

internal registers

Issue transaction

to 60x bus

(1)

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