MPC8280 datasheet(322/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-14

Freescale Semiconductor

target qualifies the address/data lines with FRAME before asserting DEVSEL. DEVSEL is asserted at or

before the clock edge at which the PCI bridge enables its TRDY, STOP, or data (for a read). DEVSEL is

not negated until FRAME is negated, with IRDY asserted and either STOP or TRDY asserted. The

exception to this is a target-abort; see Section 9.9.1.3.2, “Transaction Termination.”

As an initiator, if the PCI bridge does not see the assertion of DEVSEL within 4 clocks of FRAME, it

terminates the transaction with a master-abort as described in Section 9.9.1.3.2, “Transaction

Termination.”

9.9.1.4.2

Fast Back-to-Back Transactions

In the two types of fast back-to-back transactions, the first type places the burden of avoiding contention

on the initiator while the second places the burden on all potential targets. The PCI bridge as a target

supports both types of fast back-to-back transactions but does not support them as an initiator. The PCI

bridge as a target has the fast back-to-back enable bit hardwired to one, or enabled; see Table 9-18.

For the first type (governed by the initiator), the initiator may only run a fast back-to-back transaction to

the same target. For the second type, when the PCI bridge detects a fast-back-to-back operation and did

not drive DEVSEL in the previous cycle, it delays the assertion of DEVSEL and TRDY for one cycle to

allow the other target to get off the bus.

9.9.1.4.3

Data Streaming

The PCI bridge provides data streaming for PCI transactions to and from prefetchable memory. In other

words, when the PCI bridge is a target for a PCI initiated transaction, it supplies or accepts multiple cache

lines of data without disconnecting. For PCI transactions to non-prefetchable space, the PCI bridge

disconnects after the first data phase so that no streaming can occur.

For PCI memory reads, streaming is achieved by performing speculative reads from memory in

prefetchable space. A block of memory can be marked as prefetchable by setting the prefetch bit in the

corresponding inbound ATU (see Table 9-18) in the following cases:

•

When reads do not alter the contents of memory (reads have no side effects)

•

When reads return all bytes regardless of the byte enable signals

•

When writes can be merged without causing errors

For a memory read command or a memory read line command, the PCI bridge reads one cache line from

memory. If the PCI read or read line transaction crosses a cache line boundary, the PCI bridge starts the

read of a new cache line. For a memory read multiple command, the PCI bridge reads two cache lines from

memory. When the PCI transaction finishes the read for the first cache line, the PCI bridge performs a

speculative read of a third cache line. The PCI bridge continues this prefetching until the end of the

transaction.

For PCI writes to memory, streaming is achieved by buffering the transaction in the space available within

the I/O sequencer. This allows PCI memory writes to execute with no wait states.

A disconnect occurs if the PCI bridge runs out of buffer space on writes, or the PCI bridge cannot supply

consecutive data beats for reads within eight PCI bus clocks of each other. A disconnect also occurs if the

transaction crosses a 4K page boundary.

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