STW5098T datasheet(50/85 Pages) STMICROELECTRONICS

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Control interface and master clock

STw5098

50/85

Control interface and master clock

Unless specified, the following description applies to both entities.

6.1

Control interface I2C mode

Figure 5.

Control interface I2C format

Note:

CMOD pin tied to GND

Figure 6.

Control interface: I2C format timing

WRITE

SINGLE BYTE

START

DEVICE ADDRESSREG n ADDRESS REG n DATA IN

ACK

STOP

WRITE

MULTI BYTE

START

DEVICE ADDRESSREG n ADDRESS REG n DATA IN

ACK

STOP

REG n+m DATA IN

ACK

m+1 data bytes

CURRENT ADDR

START

DEVICE ADDRESSCurrent REG DATA OUT

ACK

NO ACK

STOP

READ

SINGLE BYTE

CURRENT ADDR

START

DEVICE ADDRESSCurrent REG DATA OUT

ACK

NO ACK

STOP

READ

MULTI BYTE

Curr REG+m DATA OUT

ACK

m+1 data bytes

START

DEVICE ADDRESSREG n ADDRESS

ACK

START

DEVICE ADDRESS

REG n DATA OUT

ACK

NO ACK

STOP

RANDOM ADDR

READ

SINGLE BYTE

RANDOM ADDR

READ

MULTI BYTE

START

DEVICE ADDRESSREG n ADDRESS

ACK

START

DEVICE ADDRESS

NO ACK

STOP

REG n+m DATA OUT

ACK ACK

m+1 data bytes

REG n DATA OUT

ACK

001 101AS1

001 101 AS1

001 101AS0

0011 01AS0

0011 01AS1

0 0110 1AS1

001 101AS0

(STO)

tSU

(STA)

tSU

(STA)

tHD

(DAT)

tSU

tHIGH

tBUF

(DAT)

tHD

tLOW

(STA)

tHD

P= STOP

S = START

Sr = START repeated

SDA

SCLK

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