GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core

©2000-2003 Genesys Logic Inc.—All rights reserved.

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5.1.2 Transmit Timing for Data Packet

Figure 5.2 - Timing Diagram of Transmit for Data Packet

The SIE negates TXVLD to complete a packet. Once negated, the Transmit State Machine will never reassert

TXRDY until after the EOP has been loaded into the Transmit Shift Register. Note that the UTM Transmit

State Machine can be ready to start another package immediately, however the SIE must confirm to the

minimum inter-packet delays identified in the USB 2.0 Specification.

5.2 Receive Operation

5.2.1 Receive State Diagram

Figure 5.3 - Receive State Diagram

Data

Data

Data

Data

CRC

CRC

PID

SYNC

PID

Data

Data

Data

Data

CRC

C

CRC

C

EOP

P

CLK30

TXVLD

Data

TXRDY

DP/DM

Reset

!RXACTV

!RXVLD

RX Wait

Trip SYNC

RXACTV

Rx Data

RXVLD

RX Data Wait

!RXVLD

Strip EOP

!RXACTV

!RXVLD

HRST#

!HRST#

SYNC Detected

Data

!Data

!SYNC

SYNC

Data

Data

Abort 1

!RXACTV

!RXVLD

!RXERR

Terminate

!RXACTV

Abort 2

!RXVLD

!RXERR

Error

RXERR

EOP

Detected

!Data

Receive

Error

!Idle

state

Idle

state