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AS8267 bảng dữ liệu(PDF) 68 Page - ams AG

tên linh kiện AS8267
Giải thích chi tiết về linh kiện  Single-Phase 2-Current Energy Measurement Integrated Circuits with Microcontroller, RTC, Programmable Multi-Purpose I/Os
PDF  136 Pages
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AS8267 bảng dữ liệu(HTML) 68 Page - ams AG

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Data Sheet AS8267 / AS8268
Revision 1.0, 19-Jun-07
Page 68 of 136
SPI Registers
Register Name
Address Description
SSPCON
9400h
Control register
SSPCLKDIV
9401h
Clock divider register
SSPSTAT
9402h
Status register
SSPBUF
9403h
Data register
Control Register (SSPCON, 9400h)
The control register is used for enabling the SPI-interrupts and to control the chip select of the SPI.
MSB
LSB
IETR
IEOV
IECO
IECS
CSO
-
AUTO
-
Bit
Symbol Function
7
IETR
Transmit interrupt enable
Issued after data register has been serially loaded with new data (slave mode) or if data has been
shifted out after write access (master mode)
0: disable
1: enable
6
IEOV
Overrun interrupt enable
Issued if ITRA still set and new data serially arrived
0: disable
1: enable
5
IECO
Write collision interrupt enable
Issued if data register is written during transmission
0: disable
1: enable
4
IECS
Chip select interrupt enable
Issued if chip-select pin is activated during master/slave mode
0: disable
1: enable
3
CSO
Chip select output state in master mode if AUTO = 0
Inverted state of output signal S_N
0: S_N = ‘1’
1: S_N = ‘0’ (active)
2
ISOUT Chip select output enable control in master mode
1
AUTO
1: Automatically activates the S_N (= ’0’) after data has been written to the data register and
deactivates S_N (= ’1’) after transfer completed
0: S_N depends on the CSO bit (
→ manual S_N setting)
0
-
Not used



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