ST7263BDX datasheet(40/145 Pages) STMICROELECTRONICS

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I/O ports (Cont’d)

10.3.5 Register description

Data registers (PxDR)

Port A Data Register (PADR): 0000h

Port B Data Register (PBDR): 0002h

Port C Data Register (PCDR): 0004h

Port D Data Register (PDDR): 0006h

Read/Write

Reset value Port A: 0000 0000 (00h)

Reset value Port B: 0000 0000 (00h)

Reset value Port C: 1111 x000 (FXh)

Reset value Port D: 0000 0000 (00h)

Note: For Port C, unused bits (7-3) are not acces-

sible.

Bit 7:0 = D[7:0] Data Register 8 bits.

The DR register has a specific behaviour accord-

ing to the selected input/output configuration. Writ-

ing the DR register is always taken into account

even if the pin is configured as an input. Reading

the DR register returns either the DR register latch

content (pin configured as output) or the digital val-

ue applied to the I/O pin (pin configured as input).

Note: When using open-drain I/Os in output con-

figuration, the value read in DR is the digital value

applied to the I/Opin.

Data Direction Register (PxDDR)

Port A Data Direction Register (PADDR): 0001h

Port B Data Direction Register (PBDDR): 0003h

Port C Data Direction Register (PCDDR): 0005h

Port D Data Direction Register (PDDDR): 0007h

Read/Write

Reset value Port A: 0000 0000 (00h)

Reset value Port B: 0000 0000 (00h)

Reset value Port C: 1111 x000 (FXh)

Reset value Port D: 0000 0000 (00h)

Note: For Port C, unused bits (7-3) are not acces-

sible

Bit 7:0 = DD[7:0] Data Direction Register 8 bits.

The DDR register gives the input/output direction

configuration of the pins. Each bit is set and

cleared by software.

0: Input mode

1: Output mode

Table 15. I/O ports register map

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