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ST7263BDX bảng dữ liệu(PDF) 90 Page - STMicroelectronics

tên linh kiện ST7263BDX
Giải thích chi tiết về linh kiện  Low speed USB 8-bit MCU family with up to 32K Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI & I짼C
PDF  145 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7263BDX bảng dữ liệu(HTML) 90 Page - STMicroelectronics

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sion. The resetting of the BUSY bit can then be
handled in a similar manner as the BERR flag
being set.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft-
ware must ensure either that the SCL line is back
at 0 before reading the SR2 register, or be able
to correctly handle a second interrupt during the
9th pulse of a transmitted byte.
– ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slave mode (the M/SL
bit is cleared).
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low if the
last bits transmitted are all 0. While AF=1, the SCL
line may be held low due to SB or BTF flags that
are set at the same time. It is then necessary to re-
lease both lines by software.



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