PI7C8152B datasheet(58/90 Pages) PERICOM

58 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 58 of 90

October 16, 2003 – Revision 1.11

When the locked delayed memory read request is queued, PI7C8152x does not queue any

more transactions until the locked sequence is finished. PI7C8152x signals a target retry to

all transactions initiated subsequent to the locked read transaction that are intended for

targets on the other side of PI7C8152x. PI7C8152x allows any transactions queued before

the locked transaction to complete before initiating the locked transaction.

When the locked delayed memory read request transaction moves to the head of the

delayed transaction queue, PI7C8152x initiates the transaction as a locked read transaction

by de-asserting LOCK_L on the target bus during the first address phase, and by asserting

LOCK_L one cycle later. If LOCK_L is already asserted (used by another initiator),

PI7C8152x waits to request access to the secondary bus until LOCK_L is de-asserted when

the target bus is idle. Note that the existing lock on the target bus could not have crossed

PI7C8152x. Otherwise, the pending queued locked transaction would not have been

queued. When PI7C8152x is able to complete a data transfer with the locked read

transaction, the lock is established on the secondary bus.

When the initiator repeats the locked read transaction on the primary bus with the same

address, transaction type, and byte enable bits, PI7C8152x transfers the read data back to

the initiator, and the lock is then also established on the primary bus.

For PI7C8152x to recognize and respond to the initiator, the initiator’s subsequent attempts

of the read transaction must use the locked transaction sequence (de-assert LOCK_L during

address phase, and assert LOCK_L one cycle later). If the LOCK_L sequence is not used in

subsequent attempts, a master timeout condition may result. When a master timeout

condition occurs, SERR_L is conditionally asserted (see Section 6.4), the read data and

queued read transaction are discarded, and the LOCK_L signal is de-asserted on the target

bus.

Once the intended target has been locked, any subsequent locked transactions initiated on

the initiator bus that are forwarded by PI7C8152x are driven as locked transactions on the

target bus.

The first transaction to establish LOCK_L must be Memory Read. If the first transaction is

not Memory read, the following transactions behave accordingly:

Type 0 Configuration Read/Write induces master abort

Type 1 Configuration Read/Write induces master abort

I/O Read induces master abort

I/O Write induces master abort

Memory Write induces master abort

When PI7C8152x receives a target abort or a master abort in response to the delayed

locked read transaction, this status is passed back to the initiator, and no locks are

established on either the target or the initiator bus. PI7C8152x resumes forwarding

unlocked transactions in both directions.

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