PI7C8152B datasheet(49/90 Pages) PERICOM

49 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 49 of 90

October 16, 2003 – Revision 1.11

Note: If parity checking is turned off and data parity errors have occurred for queued or

subsequent delayed write transactions on the initiator bus, it is possible that the initiator’s

re-attempts of the write transaction may not match the original queued delayed write

information contained in the delayed transaction queue. In this case, a master timeout

condition may occur, possibly resulting in a system error (P_SERR_L assertion).

For downstream transactions, when PI7C8152x is delivering data to the target on the

secondary bus and S_PERR_L is asserted by the target, the following events occur:

PI7C8152x sets the secondary interface data parity detected bit in the secondary status

PI7C8152x captures the parity error condition to forward it back to the initiator on the

primary bus.

Similarly, for upstream transactions, when PI7C8152x is delivering data to the target on the

primary bus and P_PERR_L is asserted by the target, the following events occur:

PI7C8152x sets the primary interface data-parity-detected bit in the status register, if

the primary parity-error-response bit is set in the command register.

PI7C8152x captures the parity error condition to forward it back to the initiator on the

secondary bus.

A delayed write transaction is completed on the initiator bus when the initiator repeats the

write transaction with the same address, command, data, and byte enable bits as the

delayed write command that is at the head of the posted data queue. Note that the parity bit

is not compared when determining whether the transaction matches those in the delayed

transaction queues.

Two cases must be considered:

When parity error is detected on the initiator bus on a subsequent re-attempt of the

transaction and was not detected on the target bus

When parity error is forwarded back from the target bus

For downstream delayed write transactions, when the parity error is detected on the

initiator bus and PI7C8152x has write status to return, the following events occur:

PI7C8152x first asserts P_TRDY_L and then asserts P_PERR_L two cycles later, if

the primary interface parity-error-response bit is set in the command register.

PI7C8152x sets the primary interface parity-error-detected bit in the status register.

Because there was not an exact data and parity match, the write status is not returned

and the transaction remains in the queue.

Similarly, for upstream delayed write transactions, when the parity error is detected on the

initiator bus and PI7C8152x has write status to return, the following events occur:

PI7C8152x first asserts S_TRDY_L and then asserts S_PERR_L two cycles later, if

the secondary interface parity-error-response bit is set in the bridge control register

(offset 3Ch).

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