C8051F331 datasheet(8/216 Pages) SILABS

8 / 216 page

C8051F330/1/2/3/4/5

Rev. 1.5

9. CIP-51 Microcontroller

Figure 9.1. CIP-51 Block Diagram ........................................................................... 73

Figure 9.2. Memory Map.......................................................................................... 79

10. Reset Sources

Figure 10.1. Reset Sources...................................................................................... 99

Figure 10.2. Power-On and VDD Monitor Reset Timing ........................................ 100

11. Flash Memory

Figure 11.1. Flash Program Memory Map.............................................................. 107

12. External RAM

13. Oscillators

Figure 13.1. Oscillator Diagram.............................................................................. 115

Figure 13.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram . 121

14. Port Input/Output

Figure 14.1. Port I/O Functional Block Diagram ..................................................... 125

Figure 14.2. Port I/O Cell Block Diagram ............................................................... 126

Figure 14.3. Crossbar Priority Decoder with No Pins Skipped ............................... 127

Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 128

15. SMBus

Figure 15.1. SMBus Block Diagram ....................................................................... 137

Figure 15.2. Typical SMBus Configuration ............................................................. 138

Figure 15.3. SMBus Transaction ............................................................................ 139

Figure 15.4. Typical SMBus SCL Generation......................................................... 143

Figure 15.5. Typical Master Transmitter Sequence................................................ 149

Figure 15.6. Typical Master Receiver Sequence.................................................... 150

Figure 15.7. Typical Slave Receiver Sequence...................................................... 151

Figure 15.8. Typical Slave Transmitter Sequence.................................................. 152

16. UART0

Figure 16.1. UART0 Block Diagram ....................................................................... 155

Figure 16.2. UART0 Baud Rate Logic .................................................................... 156

Figure 16.3. UART Interconnect Diagram .............................................................. 157

Figure 16.4. 8-Bit UART Timing Diagram............................................................... 157

Figure 16.5. 9-Bit UART Timing Diagram............................................................... 158

Figure 16.6. UART Multi-Processor Mode Interconnect Diagram .......................... 159

17. Enhanced Serial Peripheral Interface (SPI0)

Figure 17.1. SPI Block Diagram ............................................................................. 165

Figure 17.2. Multiple-Master Mode Connection Diagram ....................................... 168

Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram

168

Figure 17.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram

168

Figure 17.5. Master Mode Data/Clock Timing ........................................................ 170

Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 171

Figure 17.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 171

Figure 17.8. SPI Master Timing (CKPHA = 0)........................................................ 175

Figure 17.9. SPI Master Timing (CKPHA = 1)........................................................ 175

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