16

 2003 Semtech Corp.

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SC1480A

POWER MANAGEMENT

Application Information (Cont.)

As shown below, .B and VSSA should be routed as a differential pair to the output capacitor.

0603

0402

0402

0402

0603

0402

7343

R8

0R

0402

REFIN

1

TON

2

REFOUT

3

VCCA

4

FB

5

PGD

6

VSSA

7

PGND

8

DL

9

VDDP

10

ILIM

11

LX

12

DH

13

BST

14

U1

SC1480A

C9

1u

C8

1n

R7

10R

R6

10k0

C2

1u

+

C6

220u/15mOhm

VTT

C7

0u1

VSSA

FB

.igure 6: Differential Routing of .eedback and Ground Reference Traces

Next, looking at the power section, the schematic in .igure 7 below shows the power section. The highest di/dts

occur in the input loop (highlighted in red) and thus this loop should be kept as small as possible.

4

1

2

3

5

6

7

8

Q1

FDS6982S

C3

0u1

C1

10u

1210

0603

0402

2525

7343

R8

0R

0402

C4

2n2

VBAT

L1

2u2

+

C6

220u/15mOhm

VTT

.igure 7: Power Section and Input Loop

The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use

large copper pours to minimize parasitics and losses. See .igure 8 on Page 17 for an example.