M58PR512LE datasheet(22/119 Pages) STMICROELECTRONICS

22 / 119 page

Command interface

M58PR256LE, M58PR512LE, M58PR001LE

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4.1

Read Array command

The Read Array command returns the addressed bank to read array mode.

One bus write cycle is required to issue the Read Array command. Once a bank is in read

array mode, subsequent read operations output the data from the memory array.

A Read Array command can be issued to any banks while programming or erasing in

another bank.

If the Read Array command is issued to a bank currently executing a program or erase

operation, the bank returns to read array mode but the program or erase operation

continues. However, the data output from the bank is not guaranteed until the program or

erase operation has finished. The read modes of other banks are not affected.

4.2

Read Status Register command

The device contains a Status Register that monitors program or erase operations.

The Read Status Register command reads the contents of the Status Register for the

addressed bank.

One bus write cycle is required to issue the Read Status Register command. Once a bank is

in read Status Register mode, subsequent read operations output the contents of the Status

The Status Register data is latched on the falling edge of the Chip Enable or Output Enable

signals. Either Chip Enable or Output Enable must be toggled to update the Status Register

data.

The Read Status Register command can be issued at any time, even during program or

erase operations. The Read Status Register command only changes the read mode of the

addressed bank. The read modes of other banks are not affected. Only asynchronous read

and single synchronous read operations should be used to read the Status Register. A Read

Array command is required to return the bank to read array mode.

See Table 14 for the description of the Status Register bits.

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