9

PS8906A

08/28/07

PI3VDP411LST

Digital Video Level Shifter for dual mode DP

signals w/ inverting buffer for HPD signal

Symbol

Parameter

Min

Nom

Max

Units Comments

Single-ended

high level output

voltage

AVCC-10mV

AVCC

AVCC+10mV

V

AVCC is the DC termina-

tion voltage in the HDMI

or DVI Sink. AVCC is

nominally 3.3V

Single-ended

low level output

voltage

AVCC-600mV AVCC-500mV AVCC-400mV

V

The open-drain output

pulls down from AVcc.

Single-ended

output swing

voltage

450mV

500mV

600mV

V

Swing down from TMDS

termination voltage (3.3V

± 10%)

Single-ended

current in high-Z

state

10

μA

Measured with

TMDS outputs pulled

up to AVCC Max

(3.6V)through 50

Ω resis-

tors.

Rise time

125ps

0.4Tbit

ps

Max Rise/Fall time

@2.7Gbps = 148ps.

125ps = 148-15%

Fall time

125ps

0.4Tbit

ps

Max Rise/Fall time

@2.7Gbps = 148ps.

125ps = 148-15%

differential skew

30

ps

This differential skew

budget is in addition to

the skew presented be-

tween D+ and D- paired

input pins. HDMI revision

1.3 source allowable in-

tra-pair skew is 0.15Tbit.

to-lane output

skew

100

ps

This lane-to-lane skew

budget is in addition to

skew between differential

input pairs

Jitter added to

TMDS signals

25

ps

Jitter budget for TMDS

signals as they pass

through the level

shifter. 25ps = 0.056

Tbit at 2.25 Gb/s

TMDS Outputs

The level shifter's TMDS outputs are required to meet HMDI 1.3 specifications.

The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts

with the HDMI 1.3 specification.

Table 6: Differential Output Characteristics for TMDS_OUT signals

07-0191