5

PS8906A

08/28/07

PI3VDP411LST

Digital Video Level Shifter for dual mode DP

signals w/ inverting buffer for HPD signal

Pin Name

Type

Description

OUT_D2+

TMDS Differential output

HDMI 1.3 compliant TMDS output. OUT_D2+ makes

a differential output signal with OUT_D2–.

OUT_D2–

TMDS Differential output

HDMI 1.3 compliant TMDS output. OUT_D2– makes

a differential output signal with OUT_D2+.

OUT_D1+

TMDS Differential output

HDMI 1.3 compliant TMDS output. OUT_D1+ makes

a differential output signal with OUT_D1–.

OUT_D1–

TMDS Differential output

HDMI 1.3 compliant TMDS output. OUT_D1– makes

a differential output signal with OUT_D1+.

HPD_SINK

5V tolerance single-ended input Low Frequency, 0V to 5V (nominal) input signal. This

signal comes from the HDMI connector. Voltage High

indicates "plugged" state; voltage low indicated

"unplugged". HPD_SINK is pulled down by an

integrated 100K ohm pulldown resistor.

HPD_SOURCE# 1V buffer

Inverted buffer from 0V to 5V input signal. If input is

LOGIC HIGH, then output will be LOGIC LOW, with

VOL max of 0.1V max. If input is LOGIC LOW, then

output will be LOGIC LOW, with Voh of 0.8V min.

SCL_SOURCE

Single-ended 3.3V open-drain

DDC I/O

3.3V DDC Data I/O. Pulled up by external termina-

tion to 3.3V. Connected to SCL_SINK through volt-

age-limiting intergrated NMOS passgate.

SDA_SOURCE

Single-ended 3.3V open-drain

DDC I/O

3.3V DDC Data I/O. Pulled up by external termination

to 3.3V. Connected to SDA_SINK through voltage-

limiting intergrated NMOS passgate.

SCL_SINK

Single-ended 5V open-drain

DDC I/O

5V DDC Clock I/O. Pulled up by external termination

to 5V. Connected to SCL_SOURCE through voltage-

limiting integrated NMOS passgate.

SDA_SINK

Single-ended 5V open-drain

DDC I/O

5V DDC Data I/O. Pulled up by external termination

to 5V. Connected to SDA_SOURCE through voltage-

limiting integrated NMOS passgate.

DDC_EN

5.0V tolerant Single-ended input Enables bias voltage to the DDC passgate level shifter

gates. (May be implemented as a bias voltage connec-

tion to the DDC pass gates themselves.)

DDC_EN

Passgate

0V

Disabled

3.3V

Enabled

VCC3V

3.3V DC Supply

3.3V ± 10%

(REXT)

3.3V single-ended control input

Acceptable connections to OC_1 (REXT) pin are: Re-

sistor to GND; Resistor to 3.3V; NC. (Resistor should

be 0-ohm).

Note:

1) internal 100Kohm pull-up

07-0191