PPC440GP-3CC400CZ datasheet(49/83 Pages) AMCC

49 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

DDR SDRAM Interface

BA0:1

Bank Address supporting up to four internal banks.

2.5V SSTL_2

BankSel0:3

Selects up to four external DDR SDRAM banks.

2.5V SSTL_2

CAS

Column Address Strobe.

2.5V SSTL_2

ClkEn0:3

Clock Enable. One for each bank.

2.5V SSTL_2

DM0:8

Memory write data byte lane masks. MEMDM8 is the byte lane

mask for the ECC byte lane.

2.5V SSTL_2

DQS0:8

Byte lane data strobe. DQS8 is the data strobe for the ECC byte

lane.

I/O

2.5V SSTL_2

ECC0:7

ECC check bits 0:7.

I/O

2.5V SSTL_2

MemAddr00:12

Memory address bus.

2.5V SSTL_2

MemClkOut0

Subsystem clock.

2.5V SSTL_2

MemData00:63

Memory data bus.

I/O

2.5V SSTL_2

MemVRef1:2

Memory reference voltage (SVREF) input.

Voltage Ref

Receiver

RAS

Row Address Strobe.

2.5V SSTL_2

Write Enable.

2.5V SSTL_2

Ethernet Interface

EMCCD,

EMC1RxErr

MII: Collision detection

RMII 1: Receive error

I/O

5V tolerant

3.3V LVTTL

EMCCrS,

EMC0CrSDV

MII: Carrier sense

RMII 0: Carrier sense data valid

I/O

5V tolerant

3.3V LVTTL

EMCMDClk

MII and RMII: Management data clock

5V tolerant

3.3V LVTTL

EMCMDIO

MII and RMII: Transfer command and status information between

MII and PHY

I/O

5V tolerant

3.3V LVTTL

EMCRxD0:3,

EMC0RxD0:1,

EMC1RxD0:1

MII: Receive data

RMII 0: Receive data

RMII 1: Receive data

I/O

5V tolerant

3.3V LVTTL

EMCRxDV,

EMC1CrSDV

MII: Receive data valid

RMII 1: Carrier sense data valid

5V tolerant

3.3V LVTTL

EMCRxClk

MII: Receive clock

5V tolerant

3.3V LVTTL

EMCRxErr,

EMC0RxErr

MII: Receive error

RMII 0: Receive error

5V tolerant

3.3V LVTTL

EMCTxClk,

EMCRefClk

MII: Transmit clock

RMII: Reference clock

5V tolerant

3.3V LVTTL

EMCTxD0:3,

EMC0TxD0:1,

EMC1TxD0:1

MII: Transmit data

RMII 0: Transmit data

RMII 1: Transmit data

5V tolerant

3.3V LVTTL

Signal Functional Description (Sheet 2 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V, 10kΩ to 5V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

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