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PPC440EPX-SPAFFFTS bảng dữ liệu(PDF) 84 Page - Applied Micro Circuits Corporation |
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PPC440EPX-SPAFFFTS bảng dữ liệu(HTML) 84 Page - Applied Micro Circuits Corporation |
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84 / 94 page ![]() Notes: 1. PerClk rising edge at package pin with a 10 pF load trails the internal PLB clock by approximately 1.3ns. Signal Input (ns) Output (ns) Output Current (mA) Clock Notes Setup Time (TIS min) Hold Time (TIH min) Valid Delay (TOV max) Hold Time (TOH min) I/O H (minimum) I/O L (minimum) External Slave Peripheral Interface DMAAck0:3 n/a n/a 6 1 19.1 8.7 PerClk DMAReq0:3 4 1 n/a n/a n/a n/a PerClk EOT0:3/TC0:3 4 1 6 1 19.1 8.7 PerClk PerAddr02:31 4 1 6 1 19.1 8.7 PerClk PerBLast 4 1 6 1 19.1 8.7 PerClk PerCS0:5 n/a n/a 6 1 19.1 8.7 PerClk PerData00:15 4 1 6 1 19.1 8.7 PerClk PerData16:31 4 1 6 1 14.6 6.6 PerClk PerOE n/a n/a 6 1 19.1 8.7 PerClk PerReady 4 1 n/a n/a 19.1 8.7 PerClk PerR/W 4 1 6 1 19.1 8.7 PerClk PerWBE0:1 4 1 6 1 19.1 8.7 PerClk External Master Peripheral Interface BusReq n/a n/a 6 1 19.1 8.7 PerClk ExtAck n/a n/a 6 1 19.1 8.7 PerClk ExtReq 4 1 n/a n/a 19.1 8.7 PerClk ExtReset n/a n/a 6 1 19.1 8.7 PerClk HoldAck n/a n/a 6 1 19.1 8.7 PerClk HoldReq 4 1 n/a n/a n/a n/a PerClk HoldPri 4 1 n/a n/a n/a n/a PerClk 19.1 8.7 PLB Clk 1 PerErr 4 1 n/a n/a n/a n/a PerClk NAND Flash Interface NFALE n/a n/a 6 1 19.1 8.7 PerClk NFCE0:3 n/a n/a 6 1 19.1 8.7 PerClk NFCLE n/a n/a 6 1 19.1 8.7 PerClk NFRdyBusy 4 1 n/a n/a n/a n/a PerClk NFREn n/a n/a 6 1 19.1 8.7 PerClk NFWEn n/a n/a 6 1 19.1 8.7 PerClk 440EPx – PPC440EPx Embedded Processor Preliminary Data Sheet 84 AMCC Proprietary Revision 1.26 – October 15, 2007 Table 21. I/O Specifications—400MHz to 667MHz |
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