PPC440EP datasheet(70/84 Pages) AMCC

70 / 84 page

AMCC Proprietary

440EP – PPC440EP Embedded Processor

Revision 1.26 – April 25, 2007

Data Sheet

Table 17. I/O Specifications—333MHz to 533MHz

Notes:

1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.

Signal

Input (ns)

Output (ns)

Output Current (mA)

Clock

Notes

Setup Time

(TIS min)

Hold Time

(TIH min)

Valid Delay

(TOV max)

Hold Time

(TOH min)

I/O H

(minimum)

I/O L

(minimum)

External Slave Peripheral Interface

DMAAck0:1

n/a

5.1

6.8

PerClk

DMAAck2:3

n/a

15.3

10.2

PerClk

DMAReq0:3

11.7

0.5

n/a

PerClk

EOT0:1/TC0:1

11.7

0.5

5.1

6.8

PerClk

EOT2:3/TC2:3

11.7

0.5

15.3

10.2

PerClk

PerAddr02:31

7.2

1.5

15.3

10.2

PerClk

PerBLast

6.5

1.5

15.3

10.2

PerClk

PerCS0:5

n/a

6.5

1.5

10.3

7.1

PerClk

PerData00:15

7.2

1.5

15.3

10.2

PerClk

PerOE

n/a

6.5

1.5

15.3

10.2

PerClk

PerReady

n/a

15.3

10.2

PerClk

PerR/W

6.5

1.5

15.3

10.2

PerClk

PerWBE0:1

6.5

1.5

15.3

10.2

PerClk

External Master Peripheral Interface

BusReq

n/a

6.5

1.5

7.1

9.6

PerClk

ExtAck

n/a

6.5

1.5

7.1

9.6

PerClk

ExtReq

n/a

PerClk

ExtReset

n/a

6.0

1.5

15.3

10.2

PerClk

HoldAck

n/a

6.5

1.5

7.1

9.6

PerClk

HoldReq

n/a

PerClk

HoldPri

n/a

PerClk

n/a

15.3

10.2

PLB Clk

PerErr

n/a

10.3

7.1

PerClk

NAND Flash Interface

NFALE

n/a

6.5

1.5

5.1

6.8

NFCE0:3

n/a

6.5

1.5

10.3

7.1

NFCLE

n/a

6.5

1.5

5.1

6.8

NFRdyBusy

n/a

NFREn

n/a

6.5

1.5

5.1

6.8

NFWEn

n/a

6.5

1.5

5.1

6.8

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