PPC440EP datasheet(15/84 Pages) AMCC

15 / 84 page

AMCC Proprietary

440EP – PPC440EP Embedded Processor

Data Sheet

Revision 1.26 – April 25, 2007

General Purpose Timers (GPT)

Provides a separate time base counter and additional system timers in addition to those defined in the processor

core.

Features include:

• 32-bit Time Base Counter driven by the OPB bus clock

• Seven 32-bit compare timers

General Purpose IO (GPIO) Controller

• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master

accesses.

• 64 GPIOs are multiplexed with other functions. DCRs control whether a particular pin that has GPIO

capabilities acts as a GPIO or is used for another purpose.

• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,

tri-stated if output bit is 1).

Universal Interrupt Controller (UIC)

Two Universal Interrupt Controllers (UIC) are employed. They provide control, status, and communications

necessary between the external and internal sources of interrupts and the on-chip PowerPC processor.

Note: Processor specific interrupts (for example, page faults) do not use UIC resources.

Features include:

• 10 external interrupts

• Edge triggered or level-sensitive

• Positive or negative active

• Non-critical or critical interrupt to the on-chip processor core

• Programmable interrupt priority ordering

• Programmable critical interrupt vector for faster vector processing

JTAG

Features include:

• IEEE 1149.1 Test Access Port

• IBM RISCWatch Debugger support

• JTAG Boundary Scan Description Language (BSDL)

PPC440EP bảng dữ liệu(PDF) 15 Page - Applied Micro Circuits Corporation