440SP datasheet(80/85 Pages) AMCC

80 / 85 page

PowerPC 440SP Embedded Processor

AMCC Proprietary

Revision 1.23 - Sept 26, 2006

Data Sheet

DDR SDRAM Read Operation

The read of the incoming data from the SDRAM is done on the rising and falling edges of the differential DQS

signal. The data must be centered on these edges for correct operation.

The PPC440SP can delay in very small increments the DQS by means of the programming of the

MCIF0_RODC[RQFD] register field.

DDR SDRAM MemClkOut0 and Read Clock Delay

To accommodate timing variations introduced by the system designs using this chip, the three-stage data path

shown in Figure 9, below, is used to eliminate metastability and allow data sampling to be adjusted for minimum

latency. The data is stored in the eight Flip Flops of Stage 1, so that it can be transferred later, within an 8X period.

Figure 9. DDR SDRAM Read Data Path.

PLB bus

MCIF0_RQDC[RQFD]

Programmed

Delay

Package

Mux

Read DQS

FF: Flip-Flop

DQS

(Diff)

DDR 1X Clock

Mux

Data

(x64)

Read FIFO

PLB 1X Clock

Stage 2

Stage 1

Stage 3

PLB bus

[0:63]

[64:127]

DQS Rising

DQS Falling

(x64)

Coarse Delay

Cycles

Driver

Rec

MemDCFdbkD

MemDCFdbkR

Ext FeedBack

Read Start

Feedback

Data Capture

Window

DDR 1X Clock

MCIF0_RDCC[RDSS]

MCIF0_RFDC[RFFD]

MCIF0_RFDC[RFOS]

Stage 2 Store

Oversampling

DQS aligned

CAS Lat Delay

FeedBack

Signal Gen

Fine Delay

T1 T2 T3 T4

Fine Delay

Edge Sync

Upper

Lower

Signals

pins

Q2_Ovs

FBK signal

Delay

Compare

DDR 1X Clock

Oversampling

Clock

Read Latency adjust circuit

adjust

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