440SP datasheet(60/85 Pages) AMCC

60 / 85 page

PowerPC 440SP Embedded Processor

AMCC Proprietary

Revision 1.23 - Sept 26, 2006

Data Sheet

UART Peripheral Interface

UARTSerClk

Serial clock input that provides an alternative to the

internally generated serial clock. Used in cases where

the allowable internally generated clock rates are not

satisfactory.

3.3V LVTTL

1, 4

UART0_Rx

UART0 Receive data.

3.3V LVTTL

1, 4

UART0_Tx

UART0 Transmit data.

3.3V LVTTL

UART0_DCD

UART0 Data Carrier Detect.

3.3V LVTTL

UART0_DSR

UART0 Data Set Ready.

3.3V LVTTL

UART0_CTS

UART0 Clear To Send.

3.3V LVTTL

1, 4

UART0_DTR

UART0 Data Terminal Ready.

3.3V LVTTL

UART0_RTS

UART0 Request To Send.

3.3V LVTTL

UART0_RI

UART0 Ring Indicator.

3.3V LVTTL

w/pull-up

1, 4

UART1_Rx

UART1 Receive data.

3.3V LVTTL

1, 4

UART1_Tx

UART1 Transmit data.

3.3V LVTTL

1, 4

UART1_DSR/CTS

UART1 Data Set Ready or Clear To Send. The choice is

determined by a DCR register bit setting.

3.3V LVTTL

1, 4

UART1_DTR/RTS

UART1 Request To Send or Data Terminal Ready. The

choice is determined by a DCR register bit setting.

3.3V LVTTL

1, 4

UART2_Rx

UART2 Receive data.

3.3V LVTTL

1, 4

UART2_Tx

UART2 Transmit data.

3.3V LVTTL

1, 4

IIC Peripheral Interface

IIC0SClk

IIC0 Serial Clock.

I/O

3.3V IIC

1, 2

IIC0SDA

IIC0 Serial Data.

I/O

3.3V IIC

1, 2

IIC1SClk

IIC1 Serial Clock.

I/O

3.3V IIC

1, 2

IIC1SDA

IIC1 Serial Data.

I/O

3.3V IIC

1, 2

Interrupts Interface

IRQ0:5

External interrupt Requests 0 through 5.

3.3V LVTTL

1, 5

Table 6. Signal Functional Description (Sheet 5 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

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