PIC18F6X2X datasheet(175/386 Pages) MICROCHIP

175 / 386 page

 2003 Microchip Technology Inc.

Advance Information

DS39612A-page 173

PIC18F6X2X/8X2X

17.4.9

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the ECCPx module for PWM operation:

Configure the PWM pins PxA and PxB (and PxC

and PxD, if used) as inputs by setting the

corresponding TRIS bits.

Set the PWM period by loading the PR2 (PR4)

Configure the ECCPx module for the desired

PWM mode and configuration by loading the

CCPxCON register with the appropriate values:

• Select one of the available output

configurations and direction with the

PxM1:PxM0 bits.

• Select the polarities of the PWM output

signals with the CCPxM3:CCPxM0 bits.

Set the PWM duty cycle by loading the CCPRxL

For Half-Bridge Output mode, set the dead band

delay by loading ECCPxDEL<6:0> with the

appropriate value.

If auto shutdown operation is required, load the

ECCPxAS register:

• Select the auto shutdown sources using the

ECCPxAS2:ECCPxAS0 bits.

• Select the shutdown states of the PWM

output pins using PSSxAC1:PSSxAC0 and

PSSxBD1:PSSxBD0 bits.

• Set the ECCPxASE bit (ECCPxAS<7>).

• Configure the comparators using the CMCON

• Configure the comparator inputs as analog

inputs.

If auto restart operation is required, set the

PxRSEN bit (ECCPxDEL<7>).

Configure and start TMRn (TMR2 or TMR4):

• Clear the TMRn interrupt flag bit by clearing

the TMRnIF bit (PIR1<1> for Timer2 or

PIR3<3> for Timer4).

• Set the TMRn prescale value by loading the

TnCKPS bits (TnCON<1:0>).

• Enable Timer2 (or Timer4) by setting the

TMRnON bit (TnCON<2>).

Enable PWM outputs after a new PWM cycle

has started:

• Wait until TMRn overflows (TMRnIF bit is set).

• Enable the CCPx/PxA, PxB, PxC and/or PxD

pin outputs by clearing the respective TRIS

bits.

• Clear the ECCPASE bit (ECCPxAS<7>).

17.4.10

EFFECTS OF A RESET

Both Power-on Reset and subsequent RESETS will

force all ports to Input mode and the CCP registers to

their RESET states.

This forces the enhanced CCP module to reset to a

state compatible with the standard CCP module.

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