PIC18F6X2X datasheet(84/386 Pages) MICROCHIP

84 / 386 page

PIC18F6X2X/8X2X

DS39612A-page 82

Advance Information

 2003 Microchip Technology Inc.

EECON1 REGISTER (ADDRESS FA6h)

R/W-x

U-0

R/W-0

R/W-x

R/W-0

R/S-0

EEPGD

CFGS

—

FREE

WRERR

WREN

bit 7

bit 0

bit 7

EEPGD: FLASH Program/Data EEPROM Memory Select bit

= Access FLASH program memory

= Access data EEPROM memory

bit 6

CFGS: FLASH Program/Data EEPROM or Configuration Select bit

= Access Configuration or Calibration registers

= Access FLASH program or data EEPROM memory

bit 5

Unimplemented: Read as ‘0’

bit 4

FREE: FLASH Row Erase Enable bit

= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

= Perform write only

bit 3

WRERR: FLASH Program/Data EEPROM Error Flag bit

= A write operation is prematurely terminated

(any MCLR or any WDT Reset during self-timed programming in normal operation)

= The write operation completed

Note:

When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows

tracing of the error condition.

bit 2

WREN: FLASH Program/Data EEPROM Write Enable bit

= Allows write cycles to FLASH program/data EEPROM

= Inhibits write cycles to FLASH program/data EEPROM

bit 1

WR: Write Control bit

= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

= Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)

in software. RD bit cannot be set when EEPGD = 1.)

= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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