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PIC18F6X2X bảng dữ liệu(PDF) 140 Page - Microchip Technology |
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PIC18F6X2X bảng dữ liệu(HTML) 140 Page - Microchip Technology |
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140 / 386 page  PIC18F6X2X/8X2X DS39612A-page 138 Advance Information 2003 Microchip Technology Inc. 12.1 Timer1 Operation Timer1 can operate in one of these modes: •As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS = 0, Timer1 increments every instruc- tion cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. That is, the TRISC<1:0> value is ignored, and the pins are read as ‘0’. Timer1 also has an internal “RESET input”. This RESET can be generated by ECCP1 or ECCP2 special event trigger. This is discussed in detail in Section 12.4. FIGURE 12-1: TIMER1 BLOCK DIAGRAM FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE TMR1H TMR1L T1SYNC TMR1CS T1CKPS1:T1CKPS0 SLEEP Input FOSC/4 Internal Clock TMR1ON On/Off Prescaler 1, 2, 4, 8 Synchronize det 1 0 0 1 Synchronized Clock Input 2 TMR1IF Overflow TMR1 CLR CCP Special Event Trigger T1OSCEN Enable Oscillator(1) T1OSC Interrupt Flag Bit Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. T1OSI T1OSO/T13CKI Timer 1 TMR1L T1OSC T1SYNC TMR1CS T1CKPS1:T1CKPS0 SLEEP Input T1OSCEN Enable Oscillator(1) TMR1IF Overflow Interrupt FOSC/4 Internal Clock TMR1ON On/Off Prescaler 1, 2, 4, 8 Synchronize det 1 0 0 1 Synchronized Clock Input 2 T1OSO/T13CKI T1OSI TMR1 Flag bit Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. High Byte Data Bus<7:0> 8 TMR1H 8 8 8 Read TMR1L Write TMR1L CLR CCP Special Event Trigger |
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