NPE405L datasheet(7/54 Pages) AMCC

7 / 54 page

Preliminary

PowerNP NPe405L Embedded Processor Data Sheet

NPe405L Embedded Controller Functional Block Diagram

The NPe405L is designed using the IBM Microelectronics Blue Logic

 methodology in which major functional

blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way

to generate complex ASICs using IBM CoreConnect

 Bus Architecture.

Address Map Support

The NPe405L incorporates two separate address maps. The first is a fixed processor address map that

serves the PowerPC family of processors. This address map defines the possible contents of various address

regions which the processor can access. The second address map is for Device Configuration Registers

(DCRs). The DCRs are accessed by software running on the NPe405L processor through the use of mtdcr

and mfdcr commands.

PPC405

Processor Core

DCU

ICU

DCR Bus

16KB

On-chip Peripheral Bus (OPB)

GPIO

IIC

UART

DMA

Bridge

Processor Local Bus (PLB)

SDRAM

External

Bus

Controller

Clock

Control

Reset

Power

Mgmt

JTAG

Trace

Timers

MMU

Controller

OPB

Interrupt

Controller

Arb

28-bit addr

13-bit addr

32-bit data

Universal

I-Cache

8KB

D-Cache

(4-Channel)

DCRs

See

Peripheral

Interface

Clock Timing table

MAL0

Ethernet

HDLCEX

ZMII

MAL1

16-bit data

Two

32-channel

ports

MII,

SMII

RMII,

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