NPE405L datasheet(39/54 Pages) AMCC

39 / 54 page

Preliminary

PowerNP NPe405L Embedded Processor Data Sheet

System Interface

SysClk

Main System Clock input.

3.3V Analog

Wire w/ESD

SysReset

Main System Reset.

I/O

5V tolerant

3.3V LVTTL

1, 2

SysErr

Set to 1 when a Machine Check is generated.

5V tolerant

3.3V LVTTL

Halt

Halt from external debugger.

5V tolerant

3.3V LVTTL

GPIO00:31

General Purpose I/O. To access this function, software

must toggle a DCR bit.

I/O

5V tolerant

3.3V LVTTL

TestEn

Test Enable. Used only for manufacturing tests. Pull down

for normal operation.

3.3V LVTTL

Rcvr w/PD

TmrClk

This input must toggle at a rate of less than one half the

CPU core frequency (less than 100MHz in most cases). In

most cases this input toggles much slower (in the 1MHz to

10MHz range).

5V tolerant

3.3V LVTTL

Trace Interface

[TS1E]

[TS2E]

Even Trace execution status.To access this function,

software must toggle a DCR bit.

5V tolerant

3.3V LVTTL

[TS1O]

[TS2O]

Odd Trace execution status. To access this function,

software must toggle a DCR bit.

5V tolerant

3.3V LVTTL

[TS3:6]

Trace Status. To access this function, software must toggle

a DCR bit.

5V tolerant

3.3V LVTTL

[TrcClk]

Trace interface clock. A toggling signal that is always half

of the CPU core frequency. To access this function,

software must toggle a DCR bit.

5V tolerant

3.3V LVTTL

Power Pins

GND

Ground

Note: J09-J14, K09-K14, L09-L14, M09-M14, N09-N14,

and P09-P14 are also thermal balls.

Hardwire

VDD

Logic voltage—2.5 V

Hardwire

OVDD

Output driver voltage—3.3V

Hardwire

AVDD

Filtered PLL voltage—2.5 V

3.3V DC

Wire w/ESD

Other Pins

Reserved

Do not connect signals, voltage, or ground to these pins.

n/a

Signal Functional Description (Part 6 of 6)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.

3. Must pull down. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 31.

Signal Name

Description

I/O

Type

Notes

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