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ST72324BJ2 bảng dữ liệu(PDF) 31 Page - STMicroelectronics

tên linh kiện ST72324BJ2
Giải thích chi tiết về linh kiện  8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
PDF  188 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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ST72324BJ2 bảng dữ liệu(HTML) 31 Page - STMicroelectronics

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ST72324B
Supply, reset and clock management
31/188
Figure 15.
RESET sequences
6.5
System integrity management (SI)
The system integrity management block contains the LVD and auxiliary voltage detector
(AVD) functions. It is managed by the SICSR register.
6.5.1
LVD (low voltage detector)
The LVD function generates a static reset when the VDD supply voltage is below a VIT-
reference value. This means that it secures the power-up as well as the power-down
keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-
on in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).
The LVD reset circuitry generates a reset when VDD is below:
–VIT+ when VDD is rising
–VIT- when VDD is falling
The LVD function is illustrated in Figure 15.
The voltage threshold can be configured by option byte to be low, medium or high.
VDD
Run
RESET pin
External
Watchdog
Active phase
VIT+(LVD)
VIT-(LVD)
th(RSTL)in
Run
Watchdog underflow
tw(RSTL)out
Run
Run
reset
RESET
source
External
reset
LVD
reset
Watchdog
reset
Internal reset (256 or 4096 TCPU)
Vector fetch
Active
phase
Active
phase



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