ST72324BJ2 datasheet(183/188 Pages) STMICROELECTRONICS

183 / 188 page

ST72324B

Known limitations

183/188

Nested interrupt context

The symptom does not occur when the interrupts are handled normally, that is, when:

●

The interrupt flag is cleared within its own interrupt routine

●

The interrupt flag is cleared within any interrupt routine with higher or identical priority

level

●

The interrupt flag is cleared in any part of the code while this interrupt is disabled

If these conditions are not met, the symptom can be avoided by implementing the following

sequence:

–

PUSH CC

–SIM

–

Reset interrupt flag

–POP CC

15.1.5

16-bit timer PWM mode

In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R

the OLVL1 and OLVL2 settings.

15.1.6

TIMD set simultaneously with OC interrupt

If the 16-bit timer is disabled at the same time the output compare event occurs then output

compare flag gets locked and cannot be cleared before the timer is enabled again.

Impact on the application

If output compare interrupt is enabled, then the output compare flag cannot be cleared in the

timer interrupt routine. Consequently the interrupt service routine is called repeatedly.

Workaround

Disable the timer interrupt before disabling the timer. Again while enabling, first enable the

timer then the timer interrupts.

●

Perform the following to disable the timer:

–

TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt

–TACSR I or TBCSR I = 0x40; // Disable the timer

●

Perform the following to enable the timer again:

–

TACSR & or TBCSR & = ~0x40; // Enable the timer

–

TACR1 or TBCR1 = 0x40; // Enable the compare interrupt

15.1.7

SCI wrong break duration

Description

A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.

In some cases, the break character may have a longer duration than expected:

●

20 bits instead of 10 bits if M = 0

●

22 bits instead of 11 bits if M = 1

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