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TDA4VEN...Q1 bảng dữ liệu(PDF) 132 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  TDA4VEN, TDA4AEN Jacinto™ Processors
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TDA4VEN...Q1 bảng dữ liệu(HTML) 132 Page - Texas Instruments

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6.9.5.6 DDRSS
For more details about features and additional description information on the device LPDDR4 Memory Interface,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 6-43 and Figure 6-35 present switching characteristics for DDRSS.
Table 6-43. DDRSS Switching Characteristics
see Figure 1-1
NO.
PARAMETER
DDR TYPE
CORE VOLTAGE
MIN
MAX UNIT
1
tc(DDR_CKP/
DDR_CKN)
Cycle time, DDR_CKP and DDR_CKN
LPDDR
0.75-V Operation
0.536(1)
20
ns
0.85-V Operation
.500(1)
20
ns
(1)
Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
TI strongly recommends all designs to follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing, spacing, vias/backdrill,
PCB material, etc.) in order to achieve the full specified clock frequency. Refer to the Jacinto 7 LPDDR4 Board Design and Layout
Guidelines for details.
DDR0_CKP
1
DDR0_CKN
Figure 6-35. DDRSS Switching Characteristics
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.
TDA4VEN-Q1, TDA4AEN-Q1
SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024
www.ti.com
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