STM32F103C8 datasheet(8/67 Pages) STMICROELECTRONICS

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Description

STM32F103xx

8/67

2.2

Overview

ARM® CortexTM-M3 core with embedded Flash and SRAM

The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering

the high-performance expected from an ARM core in the memory size usually associated

with 8- and 16-bit devices.

The STM32F103xx performance line family having an embedded ARM core, is therefore

compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

Embedded Flash memory

●

Up to 128 Kbytes of embedded Flash is available for storing programs and data.

Embedded SRAM

Up to 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states.

Nested vectored interrupt controller (NVIC)

The STM32F103xx performance line embeds a Nested Vectored Interrupt Controller able to

handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex-

M3) and 16 priority levels.

●

Closely coupled NVIC gives low latency interrupt processing

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Interrupt entry vector table address passed directly to the core

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Closely coupled NVIC core interface

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Allows early processing of interrupts

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Processing of late arriving higher priority interrupts

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Support for tail-chaining

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Processor state automatically saved

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Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detectors lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect external line with pulse

width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16

external interrupt lines.

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