PM7366-PI datasheet(231/286 Pages) PMC

231 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

218

Bit

Type

Function

Default

Bit 31

R/W

PERR

Bit 30

R/W

SERR

Bit 29

R/W

MABT

Bit 28

R/W

RTABT

Bit 27

R/W

TABT

Bit 26

DVSLT[1]

Bit 25

DVSLT[0]

Bit 24

R/W

DPR

Bit 23

FBTBE

Bit 22

Bit 16

Reserved

00H

Bit 15

Bit 10

Reserved

00H

Bit 9

FBTBEN

Bit 8

R/W

SERREN

Bit 7

ADSTP

Bit 6

R/W

PERREN

Bit 5

VGASNP

Bit 4

MWAI

Bit 3

SPCEN

Bit 2

R/W

MSTREN

Bit 1

R/W

MCNTRL

Bit 0

IOCNTRL

The lower 16 bits of this register make up the Command register which provides basic control

over the GPIC's ability to respond to PCI accesses. When a 0 is written to all bits in the command

accesses. The upper 16-bits is used to record status information for PCI bus related events.

Reads to the status portion of this register behave normally. Writes are slightly different in that bits

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