PM7366-PI datasheet(95/286 Pages) PMC

95 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

TDQFE:

The transmit packet descriptor free queue write interrupt enable bit (TDQFE) enables transmit

packet descriptor free queue write interrupts to the PCI host. When TDQFE is set high,

writing a programmable number of TDRs to the TDR Free Queue will cause an interrupt to be

generated on the PCIINTB output. Interrupts are masked when TDQFE is set low. However,

the TDQFI bit remains valid when interrupts are disabled and may be polled to detect TDR

free queue write events.

TDQRDYE:

The transmit descriptor ready queue cache read interrupt enable bit (TDQRDYE) enables

transmit descriptor ready queue cache read interrupts to the PCI host. When TDQRDYE is

set high, reading a programmable number of TDRs from the TDR Ready Queue will cause an

interrupt to be generated on the PCIINTB output. Interrupts are masked when TDQRDYE is

set low. However, the TDQRDYI bit remains valid when interrupts are disabled and may be

polled to detect TDR ready queue cache read events.

TDFQEE:

The transmit descriptor free queue error interrupt enable bit (TDFQEE) enables transmit

descriptor free queue error interrupts to the PCI host. When TDFQEE is set high, attempting

to write to the transmit free queue while the queue is full will cause an interrupt to be

generated on the PCIINTB output. Interrupts are masked when TDFQEE is set low.

However, the TDFQEI bit remains valid when interrupts are disabled and may be polled to

detect TD free queue error events.

IOCE:

The transmit interrupt on complete enable bit (IOCE) enables transmission complete

interrupts to the PCI host. When IOCE is set high, complete transmission of a packet with the

IOC bit in the TD set high will cause an interrupt to be generated on the PCIINTB output.

Interrupts are masked when IOCE is set low. However, the IOCI bit remains valid when

interrupts are disabled and may be polled to detect transmission of IOC tagged packets.

TFUDRE:

The transmit FIFO underflow error interrupt enable bit (TFUDRE) enables transmit FIFO

underflow error interrupts to the PCI host. When TFUDRE is set high, attempts to read data

from the logical FIFO when it is already empty will cause an interrupt to be generated on the

PCIINTB output. Interrupts are masked when TFUDRE is set low. However, the TFUDRI bit

remains valid when interrupts are disabled and may be polled to detect transmit FIFO

underflow events.

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