ADIS16IMU5SLASHPCBZ datasheet(37/46 Pages) AD

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Data Sheet

ADIS16575/ADIS16576/ADIS16577

USER REGISTER DEFINITIONS

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FIFO Output Mode. Fresh sample data is enqueued into an

internal 512 sample FIFO. The data ready signal toggles during

enqueue, allowing sampling rate monitoring. The host system

can asynchronously pop the oldest sample data to the output

registers by reading the DIAG_STAT register.

The FIFO contains six channels of 32-bit inertial data (direct or

delta outputs as per the MSC_CTRL register, OUT_SEL bit, Bit

8), TEMP, DATA_CNTR, and TIME_STAMP. Status flags update

continuously in both modes.

FIFO mode facilitates integration with nonreal-time systems like

embedded Linux, preventing data loss. This mode offers flexibility

in data reading timing and can buffer approximately 256 ms of

samples at 4 kHz ODR. The buffering window can be extended

using the decimation filter.

The watermark interrupt allows FIFO-level monitoring without read-

ing FIFO_CNT. When enabled, this interrupt triggers based on the

samples enqueued vs. the set threshold. This interrupt supports

batch reading of multiple samples. When disabled, the WM pin is

high-Z to prevent potential damage.

FILTER CONTROL REGISTER (FILT_CTRL)

Table 115. FILT_CTRL Register Definition

Addresses

Default

Access

Flash Backup

0x5C, 0x5D

0x0000

R/W

Yes

Table 116. FILT_CTRL Bit Definitions

Bits

Description

[15:3]

Not used

[2:0]

Filter Size Variable B; number of taps in each stage; N = 2B

The FILT_CTRL register (see Table 115 and Table 116) provides

user controls for the Bartlett window FIR filter (see Figure 44),

which contains two cascaded averaging filters.

For example, use the following sequence to set Register

FILT_CTRL, Bits[2:0], = 100, which sets each stage to have 16

taps: 0xCC04 and 0xCD00.

For example, if the user wants each filter stage to have 16 taps, the

number of taps must be determined by using the N = 2B formula,

where B is the value in Bits[2:0] of the FILT_CTRL register. To solve

for B, calculate B = log2(16) = 4. In binary, this value represents

100.

To set this value in the register, follow this sequence:

1. Write 0xCC04 to the FILT_CTRL register. The 04 value sets

Bits[2:0] to 100, corresponding to B = 4. As a result, each stage

of the filter has 16 taps.

2. Write 0xCD00 to the FILT_CTRL register. This value completes

the sequence and confirms the previous setting.

After completing these steps, each stage of the filter has 16 taps,

which affects the characteristics of the filter, including its frequency

response, delay, and noise reduction capability.

Figure 70 provides the frequency response for several settings in

the FILT_CTRL register.

Figure 70. Bartlett Window, FIR Filter Frequency Response (Phase Delay = N

Samples)

RANGE IDENTIFIER (RNG_MDL)

Table 117. RNG_MDL Register Definition

Addresses

Default

Access

Flash Backup

0x5E, 0x5F

Not applicable

Table 118. RNG_MDL Bit Definitions

Bits

Description

[15:3]

Not used

[3:2]

Gyroscope measurement range

01 = ±450°/sec (ADIS16575-2, ADIS16576-2, and ADIS16577-2)

10 = reserved

00 = reserved

11 = ±2000°/sec (ADIS16576-3, and ADIS16577-3)

[1:0]

Reserved, binary value = 11

MISCELLANEOUS CONTROL REGISTER

(MSC_CTRL)

Table 119. MSC_CTRL Register Definition

Addresses

Default

Access

Flash Backup

0x60, 0x61

0x00C1

R/W

Yes

Table 120. MSC_CTRL Bit Definitions

Bits

Name

Description

[15:13] RESERVED

Not used

SENS_BW

Internal Sensor Bandwidth Selection. This bit allows the

selection between two different bandwidths for the IMUs

internal sensors.

0 = wide bandwidth: 639 Hz (gyroscope) and 750 Hz

(accelerometer),

1= medium bandwidth: ~370 Hz on accelerometers and

gyroscopes.

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