STAC9752 datasheet(34/95 Pages) IDT

34 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

5.3.1.

Slot 0: TAG / CODEC ID

Table 7. Output Slot 0 Bit Definitions

Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the

entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains

at least one time slot of valid data. The next 12 bit positions sampled by AC‘97 indicate which of the

corresponding 12 time slots contain valid data. In this way data streams of differing sample rates can

be transmitted across AC-Link at its fixed 48 KHz audio frame rate.

The two LSBs of Slot 0 transmit the CODEC ID used to distinguish Primary and Secondary CODEC

5.3.2.

Slot 1: Command Address Port

The command port is used to control features and monitor status (see AC-Link input frame Slots 1

and 2) for AC‘97 CODEC functions including, but not limited to, mixer settings, and power manage-

ment (refer to the control register section of this specification).

The control interface architecture supports up to 64 16-bit read/write registers, addressable on even

byte boundaries. Only the even registers (00h, 02h, etc.) are currently defined, odd register (01h,

03h, etc.) accesses are reserved for future expansion.

Note that shadowing of the control register file on the AC‘97 Controller is an option left open to the

implementation of the AC‘97 Controller. The AC‘97 CODEC’s control register file is nonetheless

required to be readable as well as writeable to provide more robust testability.

Bit

Description

Frame Valid

Slot 1 Primary CODEC Valid Command Address bit (Primary CODEC only)

Slot 2 Primary CODEC Valid Command Data bit (Primary CODEC only)

Slot 3-12 Valid Data bits

Slot 3: PCM Left channel

Slot 4: PCM Right channel

Slot 5: Modem Line 1 (not used on STAC9752/9753)

Slot 6: Alternative PCM1 Left

Slot 7: Alternative PCM2 Left

Slot 8: Alternative PCM2 Right

Slot 9: Alternative PCM1 Right

Slot 10: SPDIF Left

Slot 11: SPDIF Right

Slot 12: Audio GPIO

Reserved (Set to 0)

1-0

2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary)

Note: The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

STAC9752 bảng dữ liệu(PDF) 34 Page - Integrated Device Technology

STAC9752 bảng dữ liệu(HTML) 34 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

bảng dữ liệu tải về

Link URL