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M65KG512AB8W9 bảng dữ liệu(PDF) 32 Page - STMicroelectronics |
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M65KG512AB8W9 bảng dữ liệu(HTML) 32 Page - STMicroelectronics |
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32 / 54 page ![]() DC and ac parameters M65KG526AB 32/54 tDSS (4) UDQS/LDQS Falling Edge to K Setup Time 0.2 0.2 tCK tDSH (4) UDQS/LDQS Falling Edge Hold Time from K 0.2 0.2 tCK tDQSH UDQS/LDQS High Pulse Width 0.35 0.35 tCK tDQSL UDQS/LDQS Low Pulse Width 0.35 0.35 tCK tDPE tPDEN Power-Down Entry Time 2 2 tCK tDPX tPDEX Power-Down Exit Time 1 1 tCK tMRD Mode Register Set Cycle Time 2 2 tCK tPROZ (1) tHZP Precharge Command to Data Output High-Z 3 3 tCK tRPD Delay Time from Read to Precharge Command (same Bank) BL/2(2) BL/2(2) tCK tRWD Delay Time from Read to Write Command (all data output) 3+BL/2 (2) 3+BL/2 (2) tCK tRPRE Read Preamble Time 0.9 1.1 0.9 1.1 tCK tRPST Read Postamble Time 0.4 0.6 0.4 0.6 tCK tSRE tSREX Self Refresh Exit Time TJ = −30 to 85 °C 16 tCK TJ =−30 to 105 °C 22 27 tCK tWPD Delay Time from Write to Precharge Command (same Bank) 3+BL/2 (2) 3+BL/2 (3) tCK tWRD Delay Time from Write to Read Command (all data input) 2+BL/2 (2) 2+BL/2 (2) tCK tWCD Write Command to Data Input Latency 1 1 tCK tWR Write Recovery Time TJ = −30 to 85 °C 2 tCK TJ =−30 to 105 °C 3 tCK tWTR Internal Write to Read command Delay TJ = −30 to 85 °C 1 tCK TJ =−30 to 105 °C 2 2 tCK tWPRE Write Preamble 0.25 0.25 tCK tWPST (4) Data Strobe Low Pulse Width (Write Postamble) 0.4 0.6 0.4 0.6 tCK 1. CAS Latency equals 3 clock cycles. 2. BL stands for Burst Length. 3. BL stands for Burst Length. 4. The transition for Low-Z to High-Z occur when the device outputs become floating. No specific reference voltage is given in this document. Table 17. AC characteristics measured in clock period (continued) Symbol Alt Parameter M65KG512AB Unit 133MHz 166MHz Min Max Min Max |
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