CS42432-DMZ datasheet(42/59 Pages) CIRRUS

42 / 59 page

DS673F1

CS42432

7.6

ADC Control & DAC De-Emphasis (Address 05h)

7.6.1

ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE)

Default = 0

Function:

When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset

value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter

Characteristics” on page 16.

7.6.2

DAC De-Emphasis Control (DAC_DEM)

Default = 0

0 - No De-Emphasis

1 - De-Emphasis Enabled (Auto-Detect Fs)

Function:

Enables the digital filter to maintain the standard 15

μs/50μs digital de-emphasis filter response at the

auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless of

this register setting, at any other sample rate.

7.6.3

ADC1 Single-Ended Mode (ADC1 SINGLE)

Default = 0

0 - Disabled; Differential input to ADC1

1 - Enabled; Single-Ended input to ADC1

Function:

When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC1. A

+6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be driv-

en to the common mode of the ADC. See Figure 20 on page 48 for a graphical description.

543

ADC1-2_HPF

FREEZE

Reserved

DAC_DEM

ADC1

SINGLE

ADC2

SINGLE

Reserved

CS42432-DMZ bảng dữ liệu(PDF) 42 Page - Cirrus Logic