CS42432-DMZ datasheet(27/59 Pages) CIRRUS

27 / 59 page

DS673F1

CS42432

5.2

Analog Inputs

5.2.1

Line-Level Inputs

AINx+ and AINx- are the line-level differential analog inputs internally biased to VQ, approximately VA/2.

Figure 9 on page 27 shows the full-scale analog input levels. The CS42432 also accommodates single-

ended signals on all inputs, AIN1-AIN4. See “ADC Input Filter” on page 48 for the recommended input

filters.

5.2.1.1

Hardware Mode

AIN Volume Control and ADC Overflow status are not accessible in Hardware Mode.

5.2.1.2

Software Mode

For single-ended operation on ADC1-ADC2 (AIN1 to AIN4), the ADCx_SINGLE bit in the register “ADC

Control & DAC De-Emphasis (Address 05h)” on page 42 must be set appropriately (see Figure 20 on

page 48 for required external components).

The gain/attenuation of the signal can be adjusted for each AINx independently through the “AINX Volume

Control (Address 11h-14h)” on page 45. The ADC output data is in 2’s complement binary format. For in-

puts above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, re-

spectively, and cause the ADC Overflow bit in the register “Status (Address 19h) (Read Only)” on page 46

to be set to a ‘1’.

5.2.2

High-Pass Filter and DC Offset Calibration

The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation

filter. If the high-pass filter is disabled during normal operation, the current value of the DC offset for the

corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion re-

sult. This feature makes it possible to perform a system DC offset calibration by:

Status Interrupt

N/A

Hardware Mode Feature Summary

Function

Default Configuration

Hardware Control

Note

Table 2. Hardware Configurable Settings (Continued)

Full-Scale Differential Input Level =

(AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS

AINx+

AINx-

3.9 V

2.5 V

1.1 V

5.0 V

3.9 V

2.5 V

1.1 V

Figure 9. Full-Scale Input

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