PM3351-SW datasheet(49/268 Pages) PMC

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PM3351 ELAN 1X100

DATA SHEET

PMC-970113

ISSUE 3

SINGLE PORT FAST ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

ultimately by the Frame Check Sequence (FCS) word. The MAC interface unit will then

insert an interframe gap before proceeding to the next frame.

A 2-part interframe gap timing algorithm (functioning according to the IEEE 802.3

specification) is implemented. If a two-part interframe gap is not desired, it is possible to

set the Part 1 timing to zero, in which case the device will implement the Ethernet V2.0

(Blue Book) interframe gap behavior. The MAC logic also implements an internal

jabber counter to time out excessively long transmissions; thus the ELAN 1x100 does

not require the external PHY to provide jabber protection.

Half-duplex Normal Collision

In full-duplex mode, the MII signals COL (collision detect) and CRS (carrier sense) are

treated as don't cares, and have no affect on frame transmission and reception. In half-

duplex mode, however, the COL and CRS signals are used by the MAC transmit logic

to implement the required collision sensing and deference processes as outlined in the

802.3 specification.

If a collision is detected (as reported by the external PHY on the COL pin) prior to the

first 512 bits of the frame being transmitted, a normal collision is declared. The MAC

port immediately ceases frame data transmission; instead, it forces transmission of a

32-bit (8-nibble) jam sequence, flushes the transmit data disassembly registers, and

signals to the Switch Processor that a collision has occurred, as well as an indication

that a normal collision was detected. The jam sequence used by the MAC is a series of

8 nibbles with TXD[3:0] of 5 hexadecimal (0101 binary).

In response to the collision indication, the Switch Processor will load an internal backoff

timer with the appropriate pseudorandom value that denotes the backoff time to be

counted out by the MAC transmit logic. When the backoff period is timed out, the MAC

logic will automatically re-attempt transmission of the frame, which will be retained in

the transmit FIFO. If sixteen transmission attempts of a single frame have ended in

collisions, however, the Switch Processor will discard the frame and clear it from the

transmit FIFO.

Half-Duplex Late Colsion

A late collision is declared if the collision was detected after 512 bits of the Ethernet

frame, including the preamble and SFD, had already been transmitted. In this case, the

MAC will abort the transmission of the frame and send the jam sequence as usual, but

the Switch Processor will (upon notification of a late collision) cause the frame to be

dropped from the transmit FIFO and not retried. This is required as a consequence of

the dynamic re-allocation of space within the transmit FIFO; once more than 64 bytes of

a frame have been transmitted (i.e., the late collision threshold has been crossed), the

space occupied by the transmitted portion of the frame in the transmit FIFO will begin to

be continuously deallocated and used to fetch and buffer the next frame. As a result, a

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