CS5101A datasheet(20/39 Pages) CIRRUS

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CS5101A CS5102A

DS45F6

4.6.2

RBT mode is selected by tying SCKMOD high, and

OUTMOD low. As in PDT mode, SCLK is an input,

however data is available immediately following

conversion, and may be clocked out the moment

TRK1 or TRK2 falls. The falling edge of

HOLD

clears the output buffer, so any unread data will be

lost. A new conversion may be initiated before all

the data has been clocked out if the unread data

bits are not important (Figure 6).

4.6.3

Synchronous Self-clocking (SSC)

SSC mode is selected by tying SCKMOD low, and

OUTMOD high. In SSC mode, SCLK is an output,

and will clock out each bit of the data as it's being

converted. SCLK will remain high between conver-

sions, and run at a rate of 1/4 the master clock

speed for 16 low pulses during conversion

(Figure 7).

The SSH/SDL goes low coincident with the first

falling edge of SCLK, and returns high 2 CLKIN cy-

cles after the last rising edge of SCLK. This signal

frames the 16 data bits and is useful for interfacing

to shift registers (e.g. 74HC595) or to DSP serial

ports.

4.6.4

Free Run (FRN)

Free Run is the internal, synchronous loopback

mode. FRN mode is selected by tying SCKMOD

and OUTMOD low. SCLK is an output, and oper-

ates exactly the same as in the SSC mode. In Free

Run mode, the converter initiates a new conver-

sion every 80 master clock cycles, and alternates

between channel 1 and channel 2. HOLD is dis-

abled, and should be tied to either VD+ or DGND.

CH1/2 is an output, and will change at the start of

each new conversion cycle, indicating which chan-

nel will be tracked after the current conversion is

finished (Figure 8).

The SSH/SDL goes low coincident with the first

falling edge of SCLK, and returns high 2 CLKIN cy-

cles after the last rising edge of SCLK. This signal

frames the 16 data bits and is useful for interfacing

to shift registers (e.g. 74HC595) or to DSP serial

ports.

Figure 5. Pipelined Data Transmission (PDT) Mode Timing

CL K IN (i)

HOL D (i)

In te rn a l

S tatus

SC L K (i)

SD ATA (o )

C H 1/2 (i)

D15

D 14

D1 D 0 (C h. 1)

TRK 1 (o )

TRK 2 (o )

SS H /S D L (o )

C onverting C h. 2

D15

D 14

D 0 (C h. 2)

C onverting C h . 1

D15

T ra c king C h. 1

T ra c king C h. 2

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