CS4525 datasheet(47/98 Pages) CIRRUS

47 / 98 page

DS726PP1

CS4525

EQ Config register. This bit is active-low and cleared by default. To use the PWM_SIG outputs, the HiZ-

PSig bit must be set to enable the PWM_SIG output drivers.

6.1.8.1

Recommended PWM_SIG Power-Up Sequence for an External PWM

Amplifier

1. Engage the reset/power-down feature of the external PWM amplifier.

2. Set the PDnAll bit in the Power Ctrl register to stop the PWM modulators if it is not already set.

3. Configure the PWM_SIG outputs as desired via the PWMDSel[1:0] bits in the Output Cfg register.

4. Set the HiZPSig bit in the EQ Config register to activate the PWM_SIG output drivers.

5. Disengage the reset/power-down feature of the external PWM amplifier if it has an initial transition

delay feature, such as the CS4412A.

WARNING:Releasing the external amplifier from reset/power-down before PWM modulators have started

will cause a DC output on the speakers unless the external amplifier has an initial transition delay fea-

ture.

6. Clear the PDnAll bit in the Power Ctrl register to start the PWM modulators.

7. Disengage the reset/power-down feature of the external PWM amplifier if it has not been yet disen-

gaged.

6.1.8.2

Recommended PWM_SIG Power-Down Sequence for an External PWM

Amplifier

1. Mute the PWM_SIG outputs to a 50% duty-cycle by either setting Master Volume to 1111 1111h

(Master Mute) or through use of the HP_DETECT/MUTE input pin as described in the Headphone

Detection & Hardware Mute Input section on page 51.

2. Engage the reset/power-down feature of the external PWM amplifier.

3. Set the PDnAll bit in the Power Ctrl register to disable the PWM modulators and set the PWM_SIG

outputs to a drive a logic ‘0’.

4. Power down the remainder of the system (if applicable).

CS4525 bảng dữ liệu(PDF) 47 Page - Cirrus Logic