COP8SCE9HMT7 datasheet(53/70 Pages) NSC

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11.0 MICROWIRE/PLUS (Continued)

TABLE 24. MICROWIRE/PLUS

Master Mode Clock Select

SL1

SL0

SK Period

2xt

4xt

8xt

Where tC is the instruction cycle clock

11.1 MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS to start shifting the data. It gets reset

when eight data bits have been shifted. The user may reset

the BUSY bit by software to allow less than 8 bits to shift. If

enabled, an interrupt is generated when eight data bits have

been shifted. The device may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave.

Figure 29 shows how

two microcontroller devices and several peripherals may be

interconnected using the MICROWIRE/PLUS arrangements.

Warning:

The SIO register should only be loaded when the SK clock is

in the idle phase. Loading the SIO register while the SK clock

is in the active phase, will result in undefined data in the SIO

Setting the BUSY flag when the input SK clock is in the

active phase while in the MICROWIRE/PLUS is in the slave

mode may cause the current SK clock for the SIO shift

be set when the input SK clock is in the idle phase.

11.1.1 MICROWIRE/PLUS Master Mode Operation

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally. The MICROWIRE/

PLUS Master always initiates all data exchanges. The MSEL

bit in the CNTRL register must be set to enable the SO and

SK functions onto the G Port. The SO and SK pins must also

be selected as outputs by setting appropriate bits in the Port

G configuration register. In the slave mode, the shift clock

stops after 8 clock pulses.

Table 25 summarizes the bit

settings required for Master mode of operation.

11.1.2 MICROWIRE/PLUS Slave Mode Operation

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by setting and

resetting the appropriate bits in the Port G configuration

Table 25 summarizes the settings required to enter

the Slave mode of operation.

TABLE 25. MICROWIRE/PLUS Mode Settings

This table assumes that the control flag MSEL is set.

G4 (SO)

G5 (SK)

Operation

Config. Bit

Fun.

Int.

MICROWIRE/PLUS

Master

TRI-

Int.

MICROWIRE/PLUS

STATE

Master

Ext.

MICROWIRE/PLUS

Slave

TRI-

Ext.

MICROWIRE/PLUS

STATE

Slave

The user must set the BUSY flag immediately upon entering

the Slave mode. This ensures that all data bits sent by the

Master is shifted properly. After eight clock pulses the BUSY

flag is clear, the shift clock is stopped, and the sequence

may be repeated.

11.1.3 Alternate SK Phase Operation and SK Idle

Polarity

The device allows either the normal SK clock or an alternate

phase SK clock to shift data in and out of the SIO register. In

both the modes the SK idle polarity can be either high or low.

The polarity is selected by bit 5 of Port G data register. In the

normal mode data is shifted in on the rising edge of the SK

clock and the data is shifted out on the falling edge of the SK

20032735

FIGURE 29. MICROWIRE/PLUS Application

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