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PIC16F946-E/MLQTP bảng dữ liệu(PDF) 87 Page - Microchip Technology |
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PIC16F946-E/MLQTP bảng dữ liệu(HTML) 87 Page - Microchip Technology |
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87 / 330 page  © 2007 Microchip Technology Inc. DS41250F-page 85 PIC16F913/914/916/917/946 3.9.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTG pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet. 3.9.1.1 RG0/SEG36 Figure 3-30 shows the diagram for this pin. The RG0 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD 3.9.1.2 RG1/SEG37 Figure 3-30 shows the diagram for this pin. The RG1 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD 3.9.1.3 RG2/SEG38 Figure 3-30 shows the diagram for this pin. The RG2 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD 3.9.1.4 RG3/SEG39 Figure 3-30 shows the diagram for this pin. The RG3 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD 3.9.1.5 RG4/SEG40 Figure 3-30 shows the diagram for this pin. The RG4 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD 3.9.1.6 RG5/SEG41 Figure 3-30 shows the diagram for this pin. The RG5 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD FIGURE 3-30: BLOCK DIAGRAM OF RG<5:0> Data Bus WR PORTG WR TRISG RD PORTG SEG<41:36> Schmitt Trigger I/O Pin Data Latch TRIS Latch Q D Q CK Q D Q CK RD TRISG SE<41:36> and LCDEN SE<41:36> and LCDEN VDD VSS |
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